Performance Comparison of Digital Circuits Using Subthreshold Leakage Power Reduction Techniques

Complementary metal-oxide semiconductors (CMOS), stack, sleep and sleepy keeper techniques are used to control sub-threshold leakage. These effective low-power digital circuit design approaches reduce the overall power dissipation. In this paper, the characteristics of inverter, twoinput negative-AND (NAND) gate, and half adder digital circuits were analyzed and compared in 45nm, 120nm, 180nm technology nodes by applying several leakage power reduction methodologies to conventional CMOS designs. The sleepy keeper technique when compared to other techniques dissipates less static power. The advantage of the sleepy keeper technique is mainly its ability to preserve the logic state of a digital circuit while reducing subthreshold leakage power dissipation.


Introduction
Integrated circuit technology enables the innovative devices and systems that change the essence of life.The continuous development of high performance integrated circuits has led to an explosion in communication and computation systems.Major concerns with very-large-scale integration (VLSI) designs recently have shifted to power considerations along with area and speed.Power management for VLSI design has become vital due to a reduction in the geometry of transistors and also exponential growth in the number of transistors on a single chip.This trend developed because of special portable devices and applications.The change in technology has been the result of development in VLSI techniques, which has emerged as a rapidly growing technology influencing the world in encouraging innovation.Improvements in manufacturing have led to ever-smaller transistors which can accommodate a greater number of transistors on a chip.The integrated circuits industry has increased the functionality of larger chips by allowing a steady path for constantly shrinking device geometries.Each new generation has approximately doubled logic circuit density and increased performance by about 40%.
Due to advanced IC technology, the minimum feature size of VLSI circuitry continues to decrease.The feature size of transistors has entered the nano-scale region due to its shrinking capacity.The transistors with smaller feature sizes have the capability of increasing the speed of the circuit and yield of manufactured chips.The latter is due to the smaller silicon area of the chip, which lowers the average number of defects per chip.VLSI chip manufacturers effectively utilize the advantages of possible reductions in feature size by scaling (shrinking) the existing designs of integrated circuits (ICs) (Borkar 1999).The better performance and rich feature sets on a single chip have evolved with an increase in integration level.As the technology scaling has continued, many design techniques mainly from the field of power management must be employed in order to attain a balanced design to meet end user needs while maintaining the performance trend of a VLSI system.The need to dissipate low power for electronic devices in Order to conserve battery life and meet packaging reliability constraints has recently arisen.In portable devices, the reduction in power consumption is essential for improving battery life and reliability and reducing heat removal costs mainly in high performance systems.
Complementary metal oxide semiconductor (CMOS) is a technology for constructing integrated circuits.CMOS devices possess important characteristics like high noise immunity and low static power consumption.In VLSI circuits, CMOS technology has become the most frequently used technology for implementation purposes because CMOS allows for a high density of logic functions on a chip.Recently much progress has been made in estimating power dissipation; power dissipation has thereby driven the design of new low power systems, and accurate and efficient power estimation techniques have been used (Bursky 1995).CMOS transistors, as they constantly switch, dissipate power.Due to this feature, dynamic power consumption is related to the number and size of transistors and also to the rate at which they switch.When the feature size shrinks below 180nm, the transistors leak a significant amount of current even in the off state.The chips, therefore, draw static power even when they are idle.
The main challenge of VLSI design is to make a good tradeoff between performance and power for a particular application.To achieve this, the methods, which reduce power leakage, have to be adopted with conventional CMOS circuits.This paper aims to detail a method to reduce sub-threshold leakage power since it is the most dominant among all the leakages in the deep sub-micron technologies (Saini and Mishra 2012).In this paper, several leakage reduction methodologies like stack, sleep, and sleepy keeper techniques were applied with the conventional digital CMOS circuits like an inverter, a two-input NAND gate, and a half adder in 180nm, 120nm, and 45nm technologies.The performance of these circuits was evaluated among those leakage reduction techniques.
The current paper is organized as follows: Section 2 describes the kinds of power dissipation, section 3 discusses several leakage power reduction mechanisms, section 4 presents the results, and section 5 concludes the paper.

Power Dissipation
Power dissipation in CMOS circuits is generally due to dynamic dissipation and static dissipation.The total power in a circuit is given by static dynamic total P P P   (1) where P total is the total power dissipation of the circuit, P dynamic is the dynamic power consumption and P static is the static power consumption.

Dynamic Power Dissipation
The dynamic power dissipation mainly occurs due to the switching activity of the transistors and the continuous charging and discharging of the MOS capacitors.This also occurs due to short-circuit current when both pMOS and nMOS stacks are partially ON.

Static Power Dissipation
The static power dissipation is mainly due to the sub-threshold leakage current through OFF transistors, gate leakage through gate dielectric material, junction leakage from source or drain diffusions, and contention current in ratioed logic circuits.The static power exists even when the chip is not in active mode.The power is also described in terms of active, standby, and sleep modes.The power that is utilized when the chip is ON is the active power, which is dominated by switching activity.When the chip is in a non-active state, standby power exists.The standby power is set by leakage in case of halted clocks and disabled ratioed logic circuits.The sleep mode intends to avoid leakage by disconnecting the power supply to unwanted circuits on a chip.In nanometer technologies, nearly one-third of the total power is considered leakage power.
Since sub-threshold leakage is considered the most dominant of all leakages, a detailed explanation of it is given in the next section.

Subthreshold Leakage Power
Subthreshold leakage is the dominant source of static power.Subthreshold leakage or conduction occurs due to thermal emission of carriers over the potential barrier, which is set by the threshold (Boray et al. 2007).Subthreshold leakage current flows even when a transistor is nominally OFF.Sub-threshold leakage increases due to the downscaling of threshold voltages.In weak inversion, below threshold voltage the transistors are not completely OFF and the sub-threshold current relies on threshold voltage.The sub-threshold leakage increases exponentially with a decrease in threshold voltage or rises with temperature, which is a major problem for chips using low supply and threshold voltages and operating at high temperatures.The sub-threshold leakage current is given as: where 0 ds I is the current at threshold and is dependent on process and device geometry.threshold voltages and thin gate oxides are applied in nanometer processes.Except in very low power applications, leakage is insignificant at above 180 nm.In 45 nm, high-K gate dielectrics is used so that sub-threshold leakage is not dominated by gate leakage.Necessary reduction techniques are then employed to reduce sub-threshold leakage.
Static power comes from the leakage and circuits with a path from the VDD (voltage drain) to the GND (ground drain).When operated at high threshold voltages, the complementary CMOS gates dissipate almost zero static power, so the circuits consume low power.The leakage increases as feature size decreases making static power consumption dominant along with dynamic power.

Method to Measure Subthreshold Leakage Current
In a general metal-oxide-semiconductor field-effect transistor (MOSFET) sub-threshold current is found by switching off the gate terminal.The current from VDD to GND in this case is the subthreshold leakage current.The scenario is shown in Fig. 2.

Reduction Techniques of Subthreshold Leakage
The low power design is mainly to reduce the predominant factor of power dissipation.So in nanometer processes, overall leakage becomes an important design constraint (Roy et al. 2003).The sub-threshold leakage which is dominant in leakage or static power dissipation is to be reduced.The following are techniques to reduce sub-threshold leakage so that power dissipation can be decreased, which is a VLSI design constraint.

Stack Technique
The leakage trough of two or more transistors is reduced on account of the stack effect.Stacks with three or more OFF transistors have even lower leakage levels.A circuit can be stacked into two half-width size transistors but propagation delay rises with number of transistors (Johnson et al. 2002).Figure 3 shows the stack technique.In this technique, the pMOS transistors' width in the pull-up network is divided and stacked into two half-width size transistors.Similarly, the width of the nMOS transistors in the pull-down network is also divided and stacked into two half-width size transistors.The major disadvantage with this technique is that it increases the overall propagation delay.

Sleep Technique
The sleep technique uses sleep transistors with high threshold voltages.Figure 4

Sleepy Keeper Technique
The sleepy keeper technique is a statepreserving technique.It has advantageous characteristics over the sleep technique.Figure 5 describes the sleepy keeper technique.In this technique, high threshold voltage pMOS and nMOS transistors are additionally used.This is the same as the sleep technique, but the additional high threshold voltage nMOS transistor is placed parallel to the sleep transistor.Similarly, the additional high threshold voltage pMOS transistor is placed parallel to the sleep nMOS transistor.When the circuit is in sleep mode, the high threshold voltage nMOS transistor is connected to the

Results and Discussion
The performance of digital circuits like inverters, two-input NAND gates, and a half adder have been studied in the current article.MICROWIND (MICROWIND, Toulouse, France) was used for layout and simulation purposes using a BSIM4 model in 45nm, 120nm, and 180nm technologies.Stack, sleep and sleepy keeper sub-threshold reduction techniques were used to calculate dynamic power dissipation, static power dissipation, and propagation delay at 27 o C. The channel widths and lengths were maintained according to the technology node.The results were compared against the parameters obtained with conventional CMOS designs.
Figure 6 shows the layout of a conventional CMOS inverter.Table 1 compares the performance of inverter using 180, 120 and 45 nm technologies with different leakage reduction mechanisms applied on a conventional CMOS inverter (Fig. 10).However, when static dissipation reduction is required according to the application, the sleepy keeper technique is preferred over other techniques.In deep sub-micron and nanoscale technologies, this technique can be utilized for designing digital circuits with improvement in the overall static power dissipation, which is mainly due to subthreshold leakage power dissipation.As the technology node is reduced to 45nm technology, the power dissipation has reduced when compared to other technologies like 120, 180 nm.The sleepy keeper technique is thus advantageous in static power reduction along with preserving the state.

Conclusion
The performance of inverter, two-input NAND gate, and half adder digital circuits were studied for sub-threshold power leakage.Even though each and every leakage reduction mechanism has its own advantages and disadvantages, choosing a leakage reduction mechanism depends on the type of circuit and end user application.In this paper, the sleepy keeper approach was found to be the best leakage reduction mechanism for several digital circuits compared to stack and sleep approaches.The sleepy keeper approach resulted in a sub-threshold power leakage of 38%, 42.2%, and 61% for 180nm, 120nm, and 45nm technologies, respectively, for inverters.For a two-input NAND gate, the reduction in subthreshold leakage current was 38.3%, 46.9%, and 36.6% for 180nm, 120nm, and 45nm technologies, respectively.The sleepy keeper approach resulted in a sub-threshold leakage reduction of 45.6%, 35.4%, and 29.1% for 180 nm, 120 nm, and 45 nm technologies, respectively, for half adders.
Figures 7-9 correspond to the layouts of the inverter with stack, sleep, and sleepy keeper techniques, respectively, which were simulated in 45nm technology.

Figure 7 .
Figure 7. Inverter layout with stack technique in 45nm technology.

Figure 8 .
Figure 8. Inverter layout with sleep technique in 45nm technology.

Figure 9 .
Figure 9. Inverter layout with Sleepy keeper technique in 45nm technology.

Table 2 .
Two input NAND gate performance in 180, 120, 45nm technologies for different leakage reduction mechanisms.
µW Figure 12.Half adder performance in 180, 120, 45nm technologies for different leakage reduction mechanisms.From tables Table1-3, it can be observed that the sub-threshold leakage power has been reduced with sleepy keeper technique compared with the other leakage reduction mechanisms for the digital CMOS circuits like inverter, a two input NAND gate and a Half adder.But the dynamic power dissipation associated with that technique is increased due to additional high threshold voltage transistors.