NEW ASYMMETRIC 21-LEVEL INVERTER WITH REDUCED NUMBER OF SWITCHES

Multilevel inverter plays an important role in the field of modern power electronics and is widely being used for many high voltage and high power industrial and commercial applications. The objective of this paper is to design and simulate the modified asymmetric multilevel inverter topology with reduced number of switches. The proposed inverter topology synthesizes 21-level output voltage during symmetric operation using three DC voltage sources and twelve switches 8 main switches and 4 auxiliary switches. The different methods of calculating the switching angles are presented in this paper. The MATLAB/Simulink software is used to simulate the proposed inverter. The performance of the proposed inverter is analyzed and the corresponding simulation results are presented in this paper.


INTRODUCTION
To date multilevel inverters have greatly attracted many researchers due to their promising advantages for many industrial applications Meynard et al. (2002). The different advantages of multilevel inverters include lower switching frequency, lower switching losses, lower peak inverse voltage, smaller common mode voltage, lower harmonic distortion, less electromagnetic interference and high voltage capability Farakhor et al. (2015). The three main conventional multilevel inverter topologies are diode clamped or neutral point clamped (Busquets-Monge et al. 2008;Nabae et al. 1981), flying capacitor (Sadigh et al. 2010;Dargahi et al. 2014) and cascaded H-bridge with independent DC sources (Babaei et al. 2012;Babaei et al. 2015;Ramani et al. 2015). A high power rating can be achieved by the multilevel inverter. Various resources such as photovoltaic, battery and fuel cells can be used as a DC source, which can be easily interfaced for a high power and medium voltage application. In diode clamped inverter, large numbers of clamping diodes are required and regulating the capacitor voltages makes the control method more complex (Busquets-Monge et al. 2008;Nabae et al. 1981). In flying capacitor inverter, the size of the inverter is increased because of the requirement of more capacitors to achieve higher levels (Sadigh et al. 2010;Dargahi et al. 2014). Cascaded H-bridge inverter is more modular compared with other topologies. It can be easily expandable for a greater number of output voltage levels. However, to achieve higher output voltage levels, it requires a greater number of individual DC voltage sources for each module and semiconductor devices which increase the number gate drive circuit (Banaei et al. 2013;Toupchi Khosroshahi, 2014;Babaei et al. 2007;Prabaharan et al. 2015). To overcome these drawbacks, different topologies of multilevel inverters and modified pulse width modulation (PWM) methods have been developed in recent years. The PWM methods for multilevel inverters help to achieve the following objectives: easy implementation, reduced switching loss and minimum total harmonic distortion Grahame et al. (2003). The most widely used PWM techniques for multilevel inverters are the carrier based PWM techniques (Rahim et al. 2010;Jayabalan et al. 2017), selective harmonic elimination PWM (SHE-PWM) techniques Zhang et al. (2009) and the space vector based PWM techniques Vafakhah et al. (2010). Different topologies of transformer with less inverter are proposed to improve the efficiency and reduce current leakage (Thiyagarajan et al. 2016;Li et al. 2015;Islam et al. 2015). Lately, different topologies of multilevel inverters with reduced components have been developed (Karasani et al. 2016;Alishah et al. 2014;Samadaei et al. 2016;Babaei et al. 2014). These inverter topologies may be symmetric or asymmetric. However, these topologies do not considerably reduce the power switches. Hence, a new topology with reduced number of switching devices and voltage sources is proposed in this paper. Unlike the previously mentioned topologies, the proposed inverter topology reduces the total number of switches in the conduction path, thereby minimizes the switching losses.
In this paper, a modified multilevel asymmetric inverter topology with a reduced number of power switches is proposed. The proposed inverter uses three DC voltage sources and twelve switches (8 main switches and 4 auxiliary switches) to generate 21-level output voltage during asymmetric mode of operation. The different modes of operation of the proposed 21-level inverter are explained in Section-2. Section-3 presents the comparison of the proposed topology with the other existing topologies. Section-4 discusses the different methods of calculating the switching angles. The simulation results obtained using MATLAB/Simulink are explained in Section-5. The detailed conclusion is presented in Section-6. Figure 1 shows the circuit diagram of the proposed 21-level asymmetric inverter. The proposed inverter consists of 3 DC voltage sources, 8 main switches and 4 auxiliary. Here, the switches S 4 and S 5 are bidirectional and other switches are unidirectional.

PROPOSED INVERTER TOPOLOGY
The term "asymmetric" is used as magnitude since the magnitude of each DC voltage sources is different. The proposed asymmetric multilevel inverter consists of two units, namely, a level creator unit and a polarity changing unit. The level creator unit creates ten levels of positive voltage. The polarity changing unit helps to change the polarity of the voltage generated by the level creator unit. The positive levels of voltage are obtained when the switches S 9 and S 12 are turned ON and switches S 10 and S 11 are turned OFF. Similarly, the negative levels of voltage are obtained with the switches S 9 and S 12 are turned OFF and switches S 10 and S 11 are turned ON. The proposed inverter can generate 21level output voltage (i.e. 10 positive levels, 10 negative levels and 1 zero). In mode-1, S 1 and S 8 are turned ON to get level-1 voltage. To get level-2 voltage during mode-2, the switches S 4 and S 7 are tuned ON. The level-3 voltage is obtained during mode-3 where the switches S 3 and S 7 are turned ON. During mode-4 operation, the switches S 3 and S 8 are tuned ON and the level-4 voltage is obtained. The level-5 voltage is obtained during mode-5 operation. During mode-5, the switches S 2 and S 5 are ON. During mode-6, the level-6 voltage is obtained with the switches S 1 and S 5 are ON. The level-7 voltage is obtained when the switches S 1 and S 6 are ON during mode-7. The level-8 voltage is obtained when the switches S 4 and S 5 are ON and the other switches are OFF during mode-8. The voltage level-9 is obtained during mode-9 operation. In this mode, the switches S 4 and S 6 are ON. During mode-10, the level-10 voltage is obtained when the switches S 3 and S 6 are ON and the other switches are OFF. The different output levels of the proposed inverter topology with its current conduction path is shown in Fig. 2. The switching states for different output voltage levels during positive cycle of the proposed multilevel inverter is given in Table 1.

COMPARISON
The comparison of the output voltage levels with the number of DC voltage sources, the number of switches and the number of on-state switches for different topologies of multilevel inverter are given in Table 2. For the proposed inverter topology, the ratio of the number of DC sources (N dc ) to the number of levels (N) is 0.14 and the ratio of the number of switches (N S ) to the number of levels is 0.57. Therefore, it is clear that the proposed multilevel inverter uses minimum number of switches to achieve fifteen level output voltage. The proposed topology used minimum switching devices and DC voltage sources to generate 21-level output voltage waveform. In addition, the number of on-state switches for the proposed inverter topology is very minimal when compared with other topologies. For the proposed topology, the number of switches in the current conduction path is only 4. This will considerably reduce the switching losses and thereby will increase the efficiency of the proposed inverter topology.

CALCULATION OF SWITCHING ANGLES
The switching angles play a major role to reduce the of total harmonic distortion (THD) of the output voltage waveform. The different methods of calculating the switching angles for the proposed asymmetrical 21-level inverter are given below Luo et al. (2013).

Method -1
In method-1, the switching angles are distributed averagely over the range 0-90 o and are determined by,

Method -2
In method-2, the switching angles are determined by using the following equation,

Method -3
The switching angles for this method are determined by using the following equation,

Method -4
The above three methods are capable of arranging the main switching angles where the output waveform is not a sine wave. According to the sine function, a new method to determine the main switching angles were established. The main idea of this method is that when the function value increases to half to the half-height of the output level, the switch angle is set and thus a better output waveform is obtained. In this method, the main switching angles are determined by the formula given below. This method gives a better output voltage waveform compared with the other methods as the output waveform is more similar to sine wave. The switching angles corresponding to the period 0 to 90 o are called as main switching angles.
For the proposed 21-level inverter, there are ten main switching angles and these are given in Table 3. The Switching pulses obtained using the different methods are shown in Fig. 3. It is seen that only two main switches were turned on to synthesize the required output voltage at any time.

SIMULATION RESULTS
The MATLAB/Simulink simulation results of the proposed asymmetrical 21-level inverter are presented in this section. The proposed inverter consists of three DC voltage sources and eight main switches. The values of the different DC voltage sources are V 1 = 60V, V 2 = 20V and V 3 = 120V. The magnitude of the voltage sources is selected in the ratio 2:1:3. The maximum voltage obtained as 200 V (i.e. V 1 + V 2 + V 3 ). The 21-level output voltage obtained for different switching methods is shown in Fig. 4. It is seen that the output voltage waveform is triangular in shape for method-1 and method-3 as the switching angles are distributed averagely over the range 0-90 o . For method-2, the output voltage waveform is trapezoidal in shape. It is also observed that the output voltage waveform is sinusoidal for method-4. The FFT analysis of the 21level output voltage waveform for different switching methods are shown in Fig. 5. The simulation results show that the harmonic content of the 21-level output voltage waveform for the switching method-4 is less as 3.90% when compared with the other methods. However, it is observed that the fundamental output voltage for the switching method-2 is as high as 240.3 V when compared with the other switching methods. As mentioned in Section 3, method-4 gives a better output voltage waveform compared with the other methods. The comparison of the fundamental output voltage and %THD are given in Table 4. The load current waveform for the different loading conditions is shown in Fig. 6. The comparison of the THD of the load current for different loading conditions is given in Table 5. It is observed that an increase in the inductive load decreases the THD of the current waveform, however, the THD of the voltage waveform remains the same for the proposed inverter topology.

CONCLUSION
A new asymmetric type 21-level inverter with a minimum number of switches has been proposed in this paper. The main advantage of this inverter topology is using only three DC voltage sources and eight main switches to achieve 21-level output voltage during the asymmetric mode of operation as compared with other conventional topologies.
The three different methods used to calculate the switching angles are presented and the simulation results are also compared in this paper. The maximum obtained voltage is equal to the sum of the magnitude of the individual voltage. The simulation result shows that the switching angles obtained by method -4 achieves less THD compared with the other methods. However, method -2 achieves high fundamental output   voltage as compared with the other methods. The major advantage of the proposed 21-level inverter is using a minimum number of switches and hence both the cost and the size of the inverter are reduced.