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Abstract

 This paper presents a realistic test approach suitable to Design For Testability (DFT) and Built- In Self Test (BIST) environments. The approach is culminated in the form of a test simulator which is capable of providing a required goal of test for the System Under Test (SUT). The simulator uses the approach of fault diagnostics with fault grading procedure to provide the tests. The tool is developed on a common PC platform and hence no special software is required. Thereby, it is a low cost tool and hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any SUT. The developed tool incorporates a flexible Graphical User Interface (GUI) procedure and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe - reliable - testable digital logic designs.

 

Keywords

Digital system testing Built-in self test Design for testability Test vector Fault diagnosis Fault collapsing Realistic test Fault cover Iteration

Article Details

How to Cite
Ahmad, A., & Al-Abri, D. (2010). Design of a Realistic Test Simulator For a Built-In Self Test Environment. The Journal of Engineering Research [TJER], 7(2), 69–79. https://doi.org/10.24200/tjer.vol7iss2pp69-79
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