Article Sidebar

Download
PDF
Statistic
Read Counter : 601 Download : 315

Downloads

Download data is not yet available.

Main Article Content

Abstract

 This paper presents a realistic test approach suitable to Design For Testability (DFT) and Built- In Self Test (BIST) environments. The approach is culminated in the form of a test simulator which is capable of providing a required goal of test for the System Under Test (SUT). The simulator uses the approach of fault diagnostics with fault grading procedure to provide the tests. The tool is developed on a common PC platform and hence no special software is required. Thereby, it is a low cost tool and hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any SUT. The developed tool incorporates a flexible Graphical User Interface (GUI) procedure and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe - reliable - testable digital logic designs.

 

Keywords

Digital system testing Built-in self test Design for testability Test vector Fault diagnosis Fault collapsing Realistic test Fault cover Iteration

Article Details

How to Cite
Ahmad, A., & Al-Abri, D. (2010). Design of a Realistic Test Simulator For a Built-In Self Test Environment. The Journal of Engineering Research [TJER], 7(2), 69–79. https://doi.org/10.24200/tjer.vol7iss2pp69-79
Download Citation
Endnote/Zotero/Mendeley (RIS)
BibTeX

References

  1. Abdi, A., Tahoori M. B. and Emamian, E. S., 2008, "Fault Diagnosis Engineering of Digital Circuits Can Identify Vulnerable Molecules in Complex Cellular Pathways", Sci. Signal., Vol. 1(42), pp 1 - 10.
  2. Ahmad, A., 1989, "On a Design Approach for Reducing Aliasing Errors and Achieving Higher Testability Goals in Combinational Circuits", Indian Institute of Technology, Roorkee Ph. D. Thesis.
  3. Ahmad, A., 2005, "Testing of Complex Integrated Circuits (ICs) - The Bottlenecks and Solutions", Asian Journal of Information Technology, Vol. 4(9), pp. 816 - 822.
  4. Ahmad, A., Al-Abri, D., 2009, "Design of Dynamic Test Tool in the Area of Digital System Testing", Presented and Published in the Proceedings of International Conference on Computer, Communication and Power (ICCCP'09) held at Oman, pp. 1-4 (Computer and Network Systems).
  5. Ahmad, A., Al-Abri, D. and Al-Ramhi, M. M., 2006, "Design of an E-Learning Process in the Area of Digital System Testing", Presented and Published in the Proceedings of International Conference on Distance Education (ICODE2006), held at Muscat, Sultanate of Oman, March 27 - 31, 2006, pp 1-8.
  6. Ali, L. Sidek, R., Ishak, A. Alauddin, M. A., and Bambang, S. S., 2005, "Design of a Low Cost IC Tester", American Journal of Applied Science, Vo. 2(4), pp. 824 - 827.
  7. Al-Lawati, A. M. J. and Ahmad, A., 2004, "Realization of a Simplified Controllability Computation Procedure - A MATLAB-SIMULINK Based Tool", Sultan Qaboos University Journal for Scientific Research - Science and Technology, Oman, Vol. 8, pp. 131 - 143.
  8. Ahmad, A., Al-Lawati, A. M. J. and Al-Naamany, A. M., 2004, "Identification of Test Point Insertion Location via Comprehensive Knowledge of Digital System's Nodal Controllability Through a Simulated Tool", Asian Journal of Information Technology, Vol. 3(3), pp. 142 - 147.
  9. Blyzniuk, M., Cibakova, T., Gramatova, E., Kuzmicz, W., Lobur, M., Pleskacz, W., Raik, J. and Ubar, R., 2000, "Hierarchical Defect-Oriented Fault Simulation for Digital Circuits", IEEE European Test Workshop, Cascais, Portugal, pp. 151-156.
  10. Dariusz, B., 1998, "How Faults can be Simulated in Self-Testable VLSI Digital Circuits?", Proceedings EUROMICRO'98, Vol. 1, pp.10180.
  11. Devadze, S., Jutman, A., Sudnitsyn, A., Ubar, R., Wuttke, H. D., 2002, "Teaching Digital RT-Level Self-Test Using a Java Applet", 20th IEEE Conference NORCHIP'2002, Copenhagen, Denmark, pp. 322-328.
  12. Hansen, M. C., Yalcin, H. and Hayes, J. P., 1999, "Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering", IEEE Design & Test, Vol. 16(3), pp. 72 - 80.
  13. Ivask, E., Raik, J., Ubar, R., 1998, "Comparison of Genetic and Random Techniques for Test Pattern Generation", Proceedings of the 6th Baltic Electronics Conference, Tallinn, pp. 163-16.
  14. Jutman, A., Raik, J., Ubar, R., 2002, "SSBDDs: Advantageous Model and Efficient Algorithms for Digital Circuit Modeling, Simulation & Test", Proceedings of 5th International Workshop on Boolean Problems (IWSBP'02), Freiberg, Germany, pp. 157-166.
  15. Liu, Y., Su, W. and Fan, T., 2008, "The Digital Circuit Fault Diagnosis Interface Design and Realization Based on VXI", Proceedings ISECS International Colloquium on Computing, Communication, Control, and Management 2008 (CCCM '08), Guangzhou, Vol. 2, pp. 215 - 219.
  16. Su, W., Zhang, S., Xue, L., 2008, "Research and Realization of Digital Circuit Fault Probe Location Process", Proceedings International Conference on Intelligent Computation Technology and Automation 2008 (ICICTA'08), Hunan, Vo. 2, pp. 897 - 900.
  17. Ubar, R., 1998, "Dynamic Analysis of Digital Circuits with Multi-Valued Simulation", Microelectronics Journal, Elsevier Science Ltd., Vol. 29(11), pp. 821-826.
  18. Ubar, R., Jutman, A., Orasson, E., Raik, J., Wuttke, H.D., 2002, "Internet-Based Software for Teaching Test of Digital Circuits", Microelectronics Education, Marcombo U Boixareu Ed., pp. 317 - 320.
  19. Ubar, R., Orasson, E., 2003, "E-Learning Tool and Exercises for Teaching Digital Test", Proceedings of 2nd IEEE Conference on Signals, Systems, Decision and Information Technology, Sousse, Tunisia, Vol. CIT-6, pp.1 - 6.
  20. Ubar, R., Wuttke, H.D., 2001, "The DILDIS-Project - Using Applets for More Demonstrative Lectures in Digital Systems Design and Test", Proceedings of 31st ASEE/IEEE Frontiers in Education Conference, Reno, NV, USA, Abstracts, p. 83.
  21. Zorian, Y., Mourad, S., 2000, "Principles of Testing Electronic Systems",J. Wiley & Sons, Inc. New York, 2000, p. 420.