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Abstract
There are many benefits to simplifying Boolean functions before they are implemented in hardware. A reduced number of gates decreases considerably the cost of the hardware, reduces the heat generated by the chip and, most importantly, increases the speed. But no method is effective for the simplification of Boolean functions, if it involves more than six variables. This paper presents a new manual method of simplification that can be effectively applied to problems with a large number of variables.
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References
- Biswas, N. N., 1986, “Computer-Aided Minimization Procedure for Boolean Functions,” IEEE Trans. On
- Computer Aided Design, Vol. CAD-5, no. 2, pp. 303-304.
- Biswas, N. N., 1971, “Minimization of Boolean Functions,” IEEE Trans. On Computers, pp. 925-929. Brayton, R. K., Hachtel, G. D., McMullen, C. T., and Sangiovanni-Vincentelli, A. L., (1985), “Logic Minimization Algorithems for VLSI Synthesis,” Kluver Academic Publishers.
- Hong, S. J., Gain, R. G., and Ostapko, D. L., 1974, “MINI: A Heuristic Approach for Logic Minimization,” IBM J. Res. Develop, Vol. 18, pp. 443-458.
- Karnaugh, M., 1953, “The Map Method for Synthesis of Combinational Logic Circuits,” Trans. AIEE. pt I, vol. 72, no. 9, pp. 593-599.
- Malik, A. A., Robert, K., Brayton, A., Newton., R., Alberto, L., and Vincentelli, S., 1988 “A Modified Approach to Two Mano, M. M., 1979, “Digital Logic and Computer Designm” Prentice-Hall: U.S.A, pp. 72-83,102-110.
- Rhyne, V. T., Noe, P. S., McKinney, M. H., and Pooch, U. W, 1977, “A New Technique for the first Minimization of Switching Functions,” IEEE Trans.
- On Computers, Vol. C-26, No. 8, pp. 757-764.45
References
Biswas, N. N., 1986, “Computer-Aided Minimization Procedure for Boolean Functions,” IEEE Trans. On
Computer Aided Design, Vol. CAD-5, no. 2, pp. 303-304.
Biswas, N. N., 1971, “Minimization of Boolean Functions,” IEEE Trans. On Computers, pp. 925-929. Brayton, R. K., Hachtel, G. D., McMullen, C. T., and Sangiovanni-Vincentelli, A. L., (1985), “Logic Minimization Algorithems for VLSI Synthesis,” Kluver Academic Publishers.
Hong, S. J., Gain, R. G., and Ostapko, D. L., 1974, “MINI: A Heuristic Approach for Logic Minimization,” IBM J. Res. Develop, Vol. 18, pp. 443-458.
Karnaugh, M., 1953, “The Map Method for Synthesis of Combinational Logic Circuits,” Trans. AIEE. pt I, vol. 72, no. 9, pp. 593-599.
Malik, A. A., Robert, K., Brayton, A., Newton., R., Alberto, L., and Vincentelli, S., 1988 “A Modified Approach to Two Mano, M. M., 1979, “Digital Logic and Computer Designm” Prentice-Hall: U.S.A, pp. 72-83,102-110.
Rhyne, V. T., Noe, P. S., McKinney, M. H., and Pooch, U. W, 1977, “A New Technique for the first Minimization of Switching Functions,” IEEE Trans.
On Computers, Vol. C-26, No. 8, pp. 757-764.45